1. Field of the Invention
The present invention relates to a method of driving an AC type plasma display panel (an AC type PDP).
2. Description of Related Art
In recent years, PDPs have found widespread application in the fields of TV displays and computer monitors because of their superiority over liquid crystal devices in dynamic image display and their capability of color display. The PDPs have also received attention as large screen flat panel display devices for high definition TV. For higher quality display, considerable research and development have been directed toward a method of driving a PDP.
In a matrix display type PDP having a screen composed of a set of cells as display elements, a memory function is used to sustain the ON state of a cell. For example, an AC type PDP is structurally imparted with a memory function with pairs of primary electrodes covered with a dielectric layer. During displaying on a PDP of this type, the screen is subjected to progressive scanning for addressing thereby to produce charged states in cells in accordance with display data. Subsequently, a sustain voltage of alternating polarity is applied to the respective cells. In a write address mode, for example, a voltage for causing an address discharge is selectively applied to cells on each line during an addressing period to charge dielectric layers in specific cells. Each time the sustain voltage is applied during a sustain period, a discharge occurs only in cells having predetermined wall charges at the initiation of the sustain period. This is because the sustain voltage (i.e., the peak value of a sustain pulse) is adjusted to be lower than a discharge starting voltage so that an effective voltage (cell voltage) exceeds the discharge starting voltage only in the cells to which a voltage (wall voltage) resulting from the wall charges is applied in addition to the sustain voltage. If the sustain voltage is applied in a shorter cycle, seemingly continuous light emission (ON state) is obtained. Therefore, luminance is dependent on the length of the sustain period, if the sustain voltage has a constant frequency.
Normally, display data are periodically updated. In displaying television images, for example, addressing is performed K.times.k (K: the number of frames, k: the number of fields for multi-level gradation display) times per second. For the updating of the display data, charges in the respective cells should be equalized prior to the production of newly charged states to prevent the influence of the previous display. The equalization of the charges is achieved by a full screen write operation whereby a reset pulse (write voltage) with a peak value higher than the discharge starting voltage is applied at one time to all of the cells. A discharge occurs on the leading edge of the reset pulse so that greater wall charges are accumulated in the dielectric layer in each of the cells than during the sustain period. The wall voltage resulting from the accumulated wall charges cancels out the write voltage to reduce the effective voltage, resulting in a lower discharge magnitude. Thereafter, a so-called self-discharge is caused solely by the wall voltage at the completion of the application of the write voltage (on the trailing edge of the reset pulse), so that most of the wall charges disappear through neutralization. As a result, the dielectric layers over the entire screen are brought into a substantially uncharged state.
The full screen write operation mentioned above is performed to obtain a state in which the entire screen is equally charged. However, a conventional PDP has such a problem that a difference is produced in the discharge intensity between a cell with residual wall charges and a cell with substantially no residual charge on the application of the write voltage, resulting in unequal charging of the screen. More specifically, on each updating of display data, a cell put in a non-emission mode at the previous updating (referred to as "uncharged cell") is in a substantially uncharged state, while a cell put in an emission mode (referred to as "charged cell") has residual wall charges. As a result, the effective voltage in the charged cell is increased by the wall voltage added to the write voltage, so that a more intense discharge occurs in the charged cell than in the uncharged cell, increasing the charges in the charged cell. When the polarity of the write voltage is inverted, the effective voltage becomes lower than the write voltage by the magnitude of the wall voltage so that the discharge intensity in the charged cell becomes lower than that in the uncharged cell.
FIG. 10 is a graphical representation illustrating a difference in the luminous intensity between a charged cell and an uncharged cell in the conventional PDP, in which the abscissa represents the time elapsed from the application of the write voltage (leading edge of the applied pulse). As shown in FIG. 10, the peak value of the luminous intensity in the charged cell (solid line) is about seven times that of the luminous intensity in the uncharged cell (dashed line). Since the luminous intensity increases with an increase in the discharge intensity, it will be appreciated from FIG. 10 that the discharge intensity in the charged cell is much greater than that in the uncharged cell.
If the discharge intensity is excessively high in the full screen write operation, the charged area in the cell is expanded more than required, so that the wall charges will not completely disappear even if a self-discharge thereafter occurs. Conversely, if the discharge intensity is excessively low, the self-discharge will not occur due to insufficient charges with the wall charges remaining as they are. Where a driving sequence in the write address mode is employed in which addressing is performed after the whole screen is brought into the uncharged state by the self-discharge, it is necessary to accumulate proper and equal wall charges in each of the cells by the full screen write operation to ensure reliable addressing. Where a driving sequence in an erase address mode is employed in which wall charges are selectively removed by an address discharge, it is also necessary to accumulate proper and equal wall charges in each of the cells.
The removal of the wall charges may otherwise be achieved by selectively applying a driving voltage only to the charged cells, instead of applying the write voltage to each of the cells to cause an erase discharge. However, a variation in the accumulated charges makes it difficult to remove the wall charges without depending on the self-discharge. Moreover, the time required for the scanning of the screen is doubled because displaying one image requires two-step addressing for writing and erasing the image. This hinders dynamic image display with natural and smooth movements and multi-level gradation display. Hence, the PDP indispensably requires the full screen write operation in practical application thereof.